Time division multiplexing (TDM) is a method of putting multiple data streams at a lower rate into a single higher rate signal by separating the higher rate signal into N time segments. The circuit that combines signals at the source (transmitting) end of a communication link is known as a multiplexer. It accepts the input from N lower rate signals, breaks each signal into segments, and assigns the segments to the higher rate signal in a rotating, repeating sequence. The frequency of the higher rate signal is N times the frequency of the lower rate signal. At the other end of the link, the individual signals are separated out by means of a circuit called a demultiplexer. The demultiplexer regenerates each lower rate signal by extracting one segment from every N segments of the higher rate signal using the same rotating, repeating sequence used by the multiplexer. A two-way communication link requires a multiplexer/demultiplexer at each end of the link.
The Synchronous Optical Network (SONET1) and Synchronous Digital Hierarchy (SDH2) standards are two examples of TDM. In SONET, the base signal rate is 51.84 Mbps and is referred to as a STS-1 signal. Forty-eight STS-1 signals are multiplexed to form an STS-48 signal and 192 STS-1 signals are multiplexed to form an STS-192 signal and so on. The SDH standard defines a similar signal hierarchy.
Time division multiplexed switches are commonly used to cross-connect lower rate signals that are contained within a higher rate signal. The lower rate signal will be referred to as a grain. The collection of lower rate signals (i.e. grains) that form a higher rate signal is referred to as a grain group. A grain group is therefore composed of a fixed number of grains.
FIG. 1 illustrates aligned TDM channels ready for switching. In a TDM channel, data is multiplexed according to location in time. Each port in a system must be aligned to a common signal. In SONET, the alignment signal is an 8 kHz start of frame signal. A stream within a channel is identified by its offset from the signal, with an individual datum recurring every G clock ticks. The grain group size G defines the granularity of switching possible in a particular TDM system. Therefore, a data value belonging to a given channel is present every G clock ticks with each clock tick often referred to as a time slot. For example, one sample from a STS 1 signal forms each grain of SONET system. An STS-48 signal is formed from 48 such grains, and therefore, the grain group size is 48.
FIG. 2 illustrates TDM switching. In general, a switch can be any number of inputs to any number of outputs. For illustrative purposes, only switches of N inputs and N outputs (N×N) are considered herein, but the invention can be easily extended to asymmetrical switches of various numbers of input and output ports. In FIG. 2, bytes are labelled with a letter representing the input port and a number representing the byte position at the port. As can be seen in the output, bytes may be reordered to any position, may be multicast to several ports (or a single port), and bytes may be dropped. The figure shows switching of grains within a single grain group. The same switching of grains within a grain group occurs for all grain groups.
FIG. 3 illustrates the conceptual implementation of an N×N memory switch 10. Two memories 12, 14 are required with each memory having N write ports and N read ports. Ingress ports 16 write a grain group to one memory while egress ports 18 read a grain group from the other memory. The specific memory written to or read from alternates at every grain group. The ingress ports 16 write data into memory at an address that is indexed by the ingress port and timeslot numbers of the ingress grains. The egress ports 18 read data from the memory location containing the desired ingress grains thereby achieving the switching of ingress data to egress ports. The read address of the egress ports is defined by a connection memory that is configured by the user.
However, it is not practical to build fast memories with more than 3 or 4 ports. An alternative but functionally equivalent implementation of the memory switch of FIG. 3 is the output buffered switch of FIG. 4. Output buffered switch 20 implements data storage at each egress port 28 with connection memory controlled multiplexing selecting the ingress grains to store.
A major disadvantage of output buffered switch architectures is the need to connect each input to a large number of destinations. The destinations are the storage elements within each egress port and are multiplied by the number of egress ports. For large N, the wiring and the input gate capacitance of the logic circuits constitute a large set of parasitic capacitors. When the data changes from one clock cycle to the next, these capacitors must be charged and discharged. The current needed to charge and discharge the parasitic capacitors must be supplied by the external power supply. In a large TDM switch the current demand can be very large, in the order of 100 Amperes and lasts for only a short period of time. The magnitude of this current spike is proportional to the number of data bits that change state from logic high to logic low or vice versa, from one clock cycle to the next. Thus, the current demand can vary from zero, in the case where the data is constant, to maximum, in the case where all the data bits toggle.
FIG. 5 illustrates a model of a TDM switch with an external power supply. The TDM switch 30 is modeled by a variable current source (Isw) with demand profiles that vary with the changes in data, and an on-chip filtering capacitor (Csw). The power supply 32 is modeled by an ideal voltage source (Vs), an output resistance (Rs) and an inductor (Ls). The inductor models the inability of the power supply to rapidly change its current output. The capacitor (Cb) represents the PC board filtering capacitors. Parasitic inductances on the PC board are represented by the inductor (Lb).
FIG. 6 illustrates a SONET STS-48 frame, or equivalently an SDH STM-16 frame. Consider the framing bytes A1 and A2, the section trace byte J0 and the National use bytes Z0 (formerly C1 bytes). The prefix <'h> (without the angled brackets) before a value will be used herein to represent a hexadecimal number or value. The A1 bytes have a constant value of 'hF6, while the A2 bytes have a constant value of 'h28. The J0 byte is arbitrary. The Z0 bytes tend to be all-zeros in many applications. The payload bytes are assumed to have random data. From a current demand point of view, there would be no current needed to charge and discharge parasitic capacitors during the A1, A2 and Z0 bytes. There would be isolated current spikes at the A1 to A2 transition, the A2 to J0 transition and the J0 to Z0 transition. During the Payload bytes, the current demand would be at a statistical average level due to the random nature of the data.
FIG. 7 illustrates the voltage at point A of FIG. 5. During the times when payload bytes are delivered to the TDM switch, the number of transitions in the data would average to 4 bits for every byte. Consequently, the voltage at point A would settle to an average value. As one enters the 48 A1 byte times, the current demand for charging and discharging the data fanout tree would fall to zero. Since the power supply can only react very slowly to the drop in current demand, capacitor Cb would charge up and the voltage at point A rises. Similarly, the voltage would continue to rise during the A2 and Z0 byte times because of the low current demands. At the transitions between A1 and A2 bytes, the data undergoes 6 bits of changes per byte ('hF6 XOR 'h28='b11011110). Due to parasitic inductances and capacitances on the PC board, this isolated current spike leads to a voltage spike and ringing at the point A of FIG. 5. Similar voltage behaviour is also observable around the J0 byte. When random payload data resumes, the current demand returns to the average value and Cb discharges. Voltage variations can adversely affect sensitive analog circuits inside the TDM switch and in other devices residing on the same PC board. Sharp current and voltage spikes are a source of electromagnetic interference (EMI) in equipment, which needs to be squelched, as much as possible.
Telecommunication systems typically have a maximum power budget for printed circuit boards of between 100 W and 120 W. In a switch fabric card, the TDM switch component often consumes the majority of that power. These components may generate current demand spikes that are up to 100 Amperes in amplitude, and are only nanoseconds in duration. It is very expensive and complex to implement power supply systems that can both deliver the large amount of power and react to such rapid current demand changes. Typical output buffered memory switches generally have very large data fanout counts, and every ingress grain from every ingress port is forwarded to each egress port where it may be selected for output.
Known pseudo-random scramblers, or such scrambling methods, can provide a statistical bound that the number of toggled bits tends towards an average value. Pathological data patterns can mimic the scrambler leading to long periods of very high or very low toggled bits over time, and consequently periods with variations in current demand. Methods to reduce overall current demand, such as sending the true or complement form of the data, depending on which has lower transitions, are also statistical in nature. For example, when a consecutive sequence of ingress data bytes have the same value, the data would not be modified. Consequently, current demand would be at zero and the voltage would rise. When data resumes, and only 4 bits changed, there will also be no reason to modify the data. One would again get a current spike or one-half the maximum unmanaged amplitude. At the opposite end of the scale, there are techniques that maintain the current demand at maximum using dummy loads, for example. These tend to be more successful in reducing variations in current demands from cycle to cycle, but at a cost of doubling the total power consumption.
It is, therefore, desirable to provide an implementation of a switch that is capable of handling the large variations in current demands, and has improved performance within the limitations of a power supply system.